Design-Reuse

A SystemVerilog DPI Framework for Reusable Transaction Level Testing, Debug and Analysis of SoC Designs

Complex system design requires modeling, testing, debug and analysis of many levels of abstraction with varying levels of accuracy. Reuse from previous steps is important at each step of the design ...
Design-Reuse

Aldec Releases Riviera-PRO(TM) 2008.02 with VHDL 2007, SystemC 2.2 and SystemVerilog (DPI)

Riviera-PRO 2008.02 supports many features of the VHDL standard draft (IEEE P1076-2007/D4.0), recently approved by Accellera. Constructs such as new data types, subprograms and operators, matching ...
EDN

Verification IP Reuse For Complex Networking Asics

Maximizing verification IP reuse improves verification productivity. The International Technology Roadmap for Semiconductors (ITRS) projects that 75 percent of design/verification productivity ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Electronic Design

SystemVerilog Verification Spans Planning To Closure

In design verification, one size does not fit all. What works on the enterprise level may not work for the design team or individual designer, and vice versa. On the heels of its acquisition of ...
Electronics Weekly

Open standard for RISC-V verification is announced at DVCon

At this year’s (virtual) functional design and verification conference, DVCon US 2022, the RISC-V Verification Interface (RVVI) was announced by Imperas Software. The interface is available at github.