A team led by Prof. Liu Xueyan from the Institute of Geochemistry of the Chinese Academy of Sciences has developed a new ...
TechInsights and SemiWiki have published key details that Intel and TSMC disclosed about their upcoming 18A (1.8nm-class) and N2 (2nm-class) process technologies at the International Electronic ...
TSMC is on track to start high-volume production of chips on N2 (2nm-class), its first production technology that relies on gate-all-around (GAA) nanosheet transistors, in the second half of this year ...
TSMC's next-generation N2 process has officially booked its first customers: Apple, MediaTek, and AMD, with NVIDIA reportedly paying a hefty premium to get pole position for A14. Notably absent from ...
SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows have been certified to support TSMC’s new Design Rule Manual (DRM) ...
SANTA CLARA, CA, Jun. 16, 2022 – TSMC today showcased its advanced logic, specialty and 3D IC technologies at the company’s 2022 North America Technology Symposium, with the next-generation N2 process ...
TSMC revealed its plans for its N2 2nm silicon production earlier this month, and has now revealed more details about it. In addition to switching from FinFET to a gate-all-around (GAA) design using ...
Companies accelerate AI, hyperscale and mobile IC development on N3E and N2 nodes Mutual customers actively designing with N3E and N2 PDKs Cadence flows supporting TSMC’s latest nodes provide optimal ...